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Только с Юр. Лицами,
мелкий и крупный опт
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Цена по запросу
5962-8772501RA, Flip Flop D-Type Bus Interface Pos-Edge 1-Element 20-Pin CDIP Tube
Semiconductor - IC > Standard Logic > Flip Flop
| Absolute Propagation Delay Time (ns) | 48 |
| Automotive | No |
| Bus Hold | No |
| ECCN (US) | EAR99 |
| EDA / CAD Models | 5962-8772501RA by Ultra Librarian |
| EU RoHS | Not Compliant |
| HTS | 8542.39.00.60 |
| Input Signal Type | Single-Ended |
| Lead Shape | Through Hole |
| Logic Family | HCT |
| Logic Function | D-Type Bus Interface |
| Maximum High Level Output Current (mA) | -4 |
| Maximum Low Level Output Current (mA) | 4 |
| Maximum Operating Supply Voltage (V) | 5.5 |
| Maximum Operating Temperature (°C) | 125 |
| Maximum Propagation Delay Time @ Maximum CL (ns) | 30@4.5V |
| Maximum Quiescent Current (mA) | 0.008 |
| Minimum Operating Supply Voltage (V) | 4.5 |
| Minimum Operating Temperature (°C) | -55 |
| Mounting | Through Hole |
| Number of Channels per Chip | 8 |
| Number of Element Inputs | 8 |
| Number of Element Outputs | 8 |
| Number of Elements per Chip | 1 |
| Package Height | 3.56(Max) |
| Package Length | 26.92(Max) |
| Package Width | 7.62(Max) |
| Packaging | Tube |
| Part Status | Active |
| PCB changed | 20 |
| Pin Count | 20 |
| Polarity | Non-Inverting |
| PPAP | No |
| Process Technology | CMOS |
| Propagation Delay Test Condition (pF) | 50 |
| Set/Reset | Master Reset |
| Standard Package Name | DIP |
| Supplier Package | CDIP |
| Supplier Temperature Grade | Military |
| SVHC | Yes |
| SVHC Exceeds Threshold | Yes |
| Triggering Type | Positive-Edge |
| Typical Operating Supply Voltage (V) | 5 |
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