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Цена по запросу
CD4013BF3A, Flip Flop D-Type Pos-Edge 2-Element 14-Pin CDIP Tube
Standard and Specialty Logic\Standard Logic\Flip Flops
| Absolute Propagation Delay Time (ns) | 400 |
| Automotive | No |
| Bus Hold | No |
| ECCN (US) | EAR99 |
| EDA / CAD Models | CD4013BF3A by Ultra Librarian |
| EU RoHS | Not Compliant |
| HTS | COMPONENTS |
| Input Signal Type | Single-Ended |
| Lead Shape | Through Hole |
| Logic Family | CD4000 |
| Logic Function | D-Type |
| Maximum High Level Output Current (mA) | -4.2(Min) |
| Maximum Low Level Output Current (mA) | 4.2(Min) |
| Maximum Operating Supply Voltage (V) | 18 |
| Maximum Operating Temperature (°C) | 125 |
| Maximum Propagation Delay Time @ Maximum CL (ns) | 90@15V|130@10V|300@5V |
| Maximum Quiescent Current (mA) | 0.02 |
| Minimum Operating Supply Voltage (V) | 3 |
| Minimum Operating Temperature (°C) | -55 |
| Mounting | Through Hole |
| Number of Channels per Chip | 2 |
| Number of Element Inputs | 1 |
| Number of Element Outputs | 1 |
| Number of Elements per Chip | 2 |
| Package Height | 3.56(Max) |
| Package Length | 19.94(Max) |
| Package Width | 7.19(Max) |
| Packaging | Tube |
| Part Status | Active |
| PCB changed | 14 |
| Pin Count | 14 |
| Polarity | Inverting/Non-Inverting |
| PPAP | No |
| Process Technology | CMOS |
| Propagation Delay Test Condition (pF) | 50 |
| Set/Reset | Set/Reset |
| Standard Package Name | DIP |
| Supplier Package | CDIP |
| Supplier Temperature Grade | Military |
| SVHC | Yes |
| SVHC Exceeds Threshold | Yes |
| Triggering Type | Positive-Edge |
| Typical Operating Supply Voltage (V) | 15|12|9|5|3.3 |
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