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CDCU877ANMKT, Clock Drivers & Distribution 1.8-V phase-lock loop clock driver for DDR2 SDRAM applications 52-NFBGA -40 to 85
Semiconductors\Clock & Timer ICs\Clock Drivers & DistributionCDCU877 Phase-Lock Loop Clock Driver Texas Instruments CDCU877 Phase-Lock Loop Clock Driver is a high-performance, low-jitter, low-skew, zero-delay buffer. It distributes a differential clock input pair (CK, CK) to 10 differential pairs of clock outputs (Yn, Yn) and one differential pair of feedback clock outputs (FBOUT, FBOUT). The clock outputs are controlled by the input clocks (CK, CK), the feedback clocks (FBIN, FBIN), the LVCMOS control pins (OE, OS), and the analog power input (AVDD). When OE is low, the clock outputs, except FBOUT/FBOUT, are disabled while the internal PLL continues to maintain its locked-in frequency. OS (output select) is a program pin that must be tied to GND or VDD. When OS is high, OE functions as previously described. When OS and OE are both low, OE does not affect Y7/Y7, as they are free running. When AVDD is grounded, the PLL is turned off and bypassed for test purposes.
| Brand | Texas Instruments |
| Factory Pack Quantity | 250 |
| Input Type | LVCMOS |
| Manufacturer | Texas Instruments |
| Max Output Freq | 340 MHz |
| Maximum Operating Temperature | +85 C |
| Minimum Operating Temperature | -40 C |
| Moisture Sensitive | Yes |
| Mounting Style | SMD/SMT |
| Operating Supply Current | 500 uA |
| Output Type | LVCMOS |
| Package / Case | NFBGA-52 |
| Product Category | Clock Drivers & Distribution |
| Product Type | Clock Drivers & Distribution |
| Product | Clock Drivers |
| Subcategory | Clock & Timer ICs |
| Supply Voltage - Max | 1.9 V |
| Supply Voltage - Min | 1.7 V |
| Type | Phase Lock Loop Clock Driver |
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