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LS1012ASE7HKB, Microprocessors - MPU 1012A Low Power Comm Processor

Semiconductors\Embedded Processors & Controllers\Microprocessors - MPULayerscape Architecture NXP Layerscape Architecture is the underlying system architecture of the QorIQ® LS series processors. The architecture enables next-generation networks with up to 100Gb/s performance and enhanced packet processing capabilities. Design effort is simplified with a standard, open programming model and a software-aware architecture framework. This design enables customers to fully exploit the underlying hardware for maximum optimization, with the capability to easily adapt to network changes for real-time soft control over the network. A uniform hardware and software model provides the compatibility and scalability required for designing end-to-end networking equipment from home-to carrier-class products. The core-agnostic architecture incorporates the optimum core for the given application: Arm® cores or Power Architecture® cores.

Brand	NXP Semiconductors
Data Bus Width	64 bit
Data RAM Size	128 kB
Factory Pack Quantity	168
Instruction Type	Floating Point
Interface Type	I2C, I2S, JTAG, SDIO, SPI, UART
L1 Cache Data Memory	32 kB
L1 Cache Instruction Memory	32 kB
L2 Cache Instruction / Data Memory	256 kB
Manufacturer	NXP
Maximum Clock Frequency	1 GHz
Maximum Operating Temperature	+105 C
Memory Type	DDR3L
Minimum Operating Temperature	0 C
Moisture Sensitive	Yes
Mounting Style	SMD/SMT
Number of Cores	1 Core
Operating Supply Voltage	900 mV
Package / Case	VFLGA-211
Packaging	Tray
Part # Aliases	935352628557
Product Category	Microprocessors-MPU
Product Type	Microprocessors-MPU
Subcategory	Microprocessors-MPU
Watchdog Timers	Watchdog Timer
Вес, г	0.16