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Только с Юр. Лицами,
мелкий и крупный опт
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Цена по запросу
SNJ54HC175J, Flip Flop D-Type Bus Interface Pos-Edge 1-Element 16-Pin CDIP Tube
Standard and Specialty Logic\Standard Logic\Flip Flops
| Absolute Propagation Delay Time (ns) | 255 |
| Automotive | No |
| Bus Hold | No |
| ECCN (US) | EAR99 |
| EDA / CAD Models | SNJ54HC175J by Ultra Librarian |
| EU RoHS | Not Compliant |
| HTS | 8542.39.00.01 |
| Input Signal Type | Single-Ended |
| Lead Shape | Through Hole |
| Logic Family | HC |
| Logic Function | D-Type Bus Interface |
| Maximum High Level Output Current (mA) | -5.2 |
| Maximum Low Level Output Current (mA) | 5.2 |
| Maximum Operating Supply Voltage (V) | 6 |
| Maximum Operating Temperature (°C) | 125 |
| Maximum Propagation Delay Time @ Maximum CL (ns) | 150@2V|30@4.5V|26@6V |
| Maximum Quiescent Current (mA) | 0.008 |
| Minimum Operating Supply Voltage (V) | 2 |
| Minimum Operating Temperature (°C) | -55 |
| Mounting | Through Hole |
| Number of Channels per Chip | 4 |
| Number of Element Inputs | 4 |
| Number of Element Outputs | 4 |
| Number of Elements per Chip | 1 |
| Package Height | 3.56(Max) |
| Package Length | 21.34(Max) |
| Package Width | 7.62(Max) |
| Packaging | Tube |
| Part Status | Active |
| PCB changed | 16 |
| Pin Count | 16 |
| Polarity | Inverting/Non-Inverting |
| PPAP | No |
| Process Technology | CMOS |
| Propagation Delay Test Condition (pF) | 50 |
| Set/Reset | Master Reset |
| Standard Package Name | DIP |
| Supplier Package | CDIP |
| Supplier Temperature Grade | Military |
| SVHC | Yes |
| Triggering Type | Positive-Edge |
| Typical Operating Supply Voltage (V) | 5 |
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